1. Field of the Invention
This invention relates to integrated circuits, and more particularly to anti-fuse structures for programmable integrated circuits.
2. Background of the Related Art
Programmable integrated circuits include such devices as field-programmable gate arrays and programmable read-only memories (PROMS). Such devices include elements such as anti-fuses to enable them to be programmed.
Field programmable gate arrays include a large number of logic elements, such as AND gates and OR gates, which can be selectively coupled together by devices like anti-fuses to perform user-designed functions. The several types of PROMS, including standard, write-once PROMS, erasable programmable read-only memories (EPROMS), electrically erasable programmable read-only memories (EEPROMS), etc., usually comprise an array of memory cells arranged in rows and columns which can be programmed to store user data. An unprogrammed anti-fuse gate array or PROM is programmed by causing selected anti-fuses to become conductive.
Anti-fuses include a material which initially has a high resistance but which can be converted into a low resistance material by the application of a programming voltage. For example, amorphous silicon, which has an intrinsic resistivity of approximately 1 megohms-cm, can be fashioned into 1 micron wide vias having a resistance of approximately 1-2 gigohms. These vias can then be melted and recrystallized by the application of a voltage in the range of 10-12 volts d.c. to form vias having a resistance less than 200 ohms. These low resistance vias can couple together logic elements of a field programmable gate array so that the gate array will perform user-defined functions, or can serve as memory cells of a PROM.
An anti-fuse device is typically formed on a semiconductor wafer by first providing a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer, each layer on top of the previous. Typically, two types of holes or vias are formed in the second insulating layer: fuse vias and link vias. Fuse vias include an anti-fuse layer and are programmed with voltages to provide the user-defined functions or memory cells as described above. Link vias are formed to provide a link to the second conductive layer, and thus do not include an anti-fuse layer.
Anti-fuses are formed within fuse vias by first depositing anti-fuse material on the insulating layer. Next, unwanted anti-fuse material is removed from the link vias and the open areas surrounding the vias. A mask material is deposited on the anti-fuse material in the fuse vias and the uncovered anti-fuse material is subjected to an etching process. The result is an anti-fuse layer provided within the fuse vias and no anti-fuse material in the link vias or open areas of the device. Finally, a third conductive layer is deposited in the fuse vias to provide a means of programming the anti-fuse material and in the link via to provide a contact to the second conductive layer.
A problem with anti-fuses is that the anti-fuse material in the fuse vias tends to have imperfections or creases known as "cusps". These cusps are weak points in the anti-fuse material and can result in the failure of the anti-fuse structure or cause the anti-fuse to be programmed by a lower programming voltage than the desired voltage.
A solution to the cusps in the anti-fuse material is to deposit a spacer layer made of an insulating material on top of the anti-fuse layer and to etch the spacer layer to form protective spacers within the vias that cover the cusps. The spacers prevent a lower programming voltage from accidentally making an anti-fuse conductive at the cusps.
The prior art has addressed the problem of cusps. In U.S. Pat. No. 5,120,679 by Boardman et al., an anti-fuse structure is disclosed in which oxide spacers are deposited within and line the walls of anti-fuse vias to prevent failure of the anti-fuse and to prevent undesired programming voltages from programming the anti-fuse. The disclosure of U.S. patent application Ser. No. 5,120,679, which is assigned to the assignee of the present invention, is hereby incorporated by reference herein in its entirety.
A problem with the use of spacers on the anti-fuse material is shown in FIG. 1. The anti-fuse device 10 includes fuse vias 12 and a link via 14. Anti-fuse material 16 is included in the fuse vias 12 but has been etched away from the link via 14 and the open areas 18 of the device. Insulating spacers 20 are provided in the fuse vias 12, where they are required to protect the cusps 22. However, spacers 24 or "dog ears" also are present in the link via 14, where they are unwanted. These spacers 24 interfere with the conductive layer that is later deposited on the vias, resulting in a poor electrical contact with the conductive layer 25.
A further problem with the use of spacers is shown in FIG. 2, which shows a via structure after the spacer layer 26 has been deposited using a typical deposition process. The spacer layer has a thickness of d1 in the via and a thickness of d2 on the open surfaces of the wafer. To form the spacers in the via, the spacer layer must be etched, and this spacer etch clears the thinner spacer material 28 in the via before the spacer material on the open areas 29. The spacer layer of thickness d2 must be completely etched away so that the following anti-fuse layer etch can be accomplished; if the spacer layer is etched only to the level d1, the leftover spacer material on the open areas 29 will interfere with the sensitive anti-fuse layer etch. However, by etching the entire thickness d2, a portion of the anti-fuse layer 16 in the via is also etched. The anti-fuse layer in the via has a thickness d3 before the spacer etch, and a thickness d4 after the spacer etch. This thinning of the anti-fuse layer is undesirable since, as a result, the programming voltage of the anti-fuse is lowered.
The method disclosed in the Boardman et al. patent provides for removing unwanted spacer material from areas outside the anti-fuse via locations, such as against vertical surfaces of the anti-fuse structure. The patent discloses using a second etch process before or after the anti-fuse material etch. However, the method in this patent does not present a solution for the thinning of the anti-fuse layer resulting from overetching the spacer layer in the via, as described above. The method in the patent presumably uses this prior art method of overetching the spacer layer to prevent excess oxide material from interfering with the anti-fuse layer etch, resulting in a lower, unpredictable programming voltage.
What is needed is a method that allows the use of insulating spacers in anti-fuse vias while substantially eliminating the problem of thinning of the anti-fuse layer in the fuse vias due to overetch of the spacer layer, thereby preventing a lower, undesired programming voltage of the anti-fuse.